J-K Datasheet(PDF) - DM74ALS109A - Fairchild Semiconductor

제조업체	부품명	데이터시트	상세설명
Fairchild Semiconductor	DM74ALS109A	55Kb/6P	Dual J-K Positive-Edge-Triggered Flip-Flop
	74VHC112	70Kb/7P	Dual J-K Flip-Flops with Preset and Clear
	MM74C73	64Kb/6P	Dual J-K Flip-Flops with Clear and Preset
	74VHC112MX	269Kb/9P	Dual J-K Flip-Flops with Preset and Clear
	74VHC112	268Kb/9P	Dual J-K Flip-Flops with Preset and Clear
	MM74C73	85Kb/7P	Dual J-K Flip-Flops with Clear and Preset
	CD4027BCN	68Kb/6P	Dual J-K Master/Slave Flip-Flop with Set and Reset
	74LVX112	77Kb/7P	Low Voltage Dual J-K Flip-Flops with Preset and Clear
	DM7473	39Kb/3P	Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
	DM7476	47Kb/4P	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
	DM7476	41Kb/4P	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
	74LCX112	99Kb/9P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
	74LCX112MTCX	102Kb/9P	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
	DM74LS109A	52Kb/5P	Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
	DM74LS73A	53Kb/5P	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
	DM74LS112A	52Kb/5P	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
	DM74S112	43Kb/4P	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
	RMPA1765	534Kb/8P	K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge Power Amplifier Module
	RMPA1765	578Kb/8P	K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge Power Amplifier Module
	AN-5241	506Kb/5P	Guidelines for Pb-Free Soldering of Fairchild Components Based on JEDEC J-STD 20D / IEC EN 61760-1 2006

J-K 데이터시트, PDF

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