제조업체 | 부품명 | 데이터시트 | 상세설명 |
Winbond
|
W631GG6KB-15 |
3Mb/158P |
Double Data Rate architecture: two data transfers per clock cycle |
Elite Semiconductor Mem...
|
M13L2561616A-2A |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
Unisonic Technologies
|
UC2000DG-AG6-R |
202Kb/5P |
Cycle-by-Cycle current limiting |
Winbond
|
W9412G2IB4 |
832Kb/50P |
Double Data Rate architecture; two data transfers per clock cycle |
W9412G6JH-5 |
1Mb/53P |
Double Data Rate architecture; two data transfers per clock cycle |
Elite Semiconductor Mem...
|
M13S2561616A-2A |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
Winbond
|
W972GG6JB-25 |
1Mb/87P |
Double Data Rate architecture: two data transfers per clock cycle |
W9725G6JB25I |
1Mb/86P |
Double Data Rate architecture: two data transfers per clock cycle |
Elite Semiconductor Mem...
|
M13S64164A-2Y |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
M13S128168A-2N |
720Kb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
M13S128324A-2M |
1Mb/48P |
Double-data-rate architecture, two data transfers per clock cycle |
M13S5121632A-2S |
705Kb/48P |
Double-data-rate architecture, two data transfers per clock cycle |
M13S2561616A-2S |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
Winbond
|
W9751G6KB-25 |
1Mb/87P |
Double Data Rate architecture: two data transfers per clock cycle |
Elite Semiconductor Mem...
|
M13L32321A-2G |
1Mb/48P |
Double-data-rate architecture, two data transfers per clock cycle |
Unisonic Technologies
|
UD38251G-SH2-R |
274Kb/7P |
Cycle-by-Cycle Over Current Protection |
International Rectifier
|
IR1153S |
386Kb/20P |
Cycle by cycle peak current limit |
NEC
|
UPD4482163 |
300Kb/28P |
8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
Elite Semiconductor Mem...
|
M14D2561616A-2E |
1Mb/61P |
Internal pipelined double-data-rate architecture; two data access per clock cycle |
M14D128168A-2M |
1,023Kb/59P |
Internal pipelined double-data-rate architecture; two data access per clock cycle |